SIMD Core and Emmy Award Winning Algorithims for Video Processing on FPGA's
In partnership with
In partnership with Geo Semiconductor, Nextera Video is now authorized to license all Realta IP, including the linearly scalable SIMD architecture (RTL if desired), the award-winning algorithms, and the programming tools to the broadcast and professional media space.
The Realta 2 FPGA Core is the result of 30 years of processor evolution and over $250 Million in development resulting in the world’s rst real-time programmable video processor. Originating at Lockheed Martin in the 1980’s, this technology was spun into Teranex, which was acquired by Silicon Optix in 2004. Silicon Optix developed the single chip Realta™ SoC, which won critical acclaim in broadcast and prosumer electronics, setting a new standard for video processing quality.
Teranex and Silicon Optix won a Technical Emmy for this groundbreaking development. In 2009, Geo Semiconductor acquired the rights to the Realta IP, and has developed a next generation core optimized for FPGAs.
Two-Dimensional Array of PE's
The Realta 2 SIMD image processing architecture mirrors the two-dimensional data structure of images. It achieves maximum inter-processor communication efficiency with direct nearest neighbor (i.e., north, south, east, west) PE connections, as shown in the Figure below, to form a fine-grained, pixel-to-processor mapping between the computer architecture and the image data structure.
Fine Grained Processor Grid Array is an Ideal Match for Fine Grained, Grid Data Structure of Images
SIMD Technical Advantages
The SIMD Core architecture is higher performance and a smaller footprint than conventional processors and DSPs for the following reasons:
Arithmetic Efficiency – Can process data at 1, 4, 8, 11, 20, 36, etc. bits per pixel with no overhead.
Linear Scalability – Doubling the array size exactly doubles the performance.
Concurrent I/O - Keeps the SIMD Engine fully utilized.
High-speed local memory – 6,144-bit wide path to memory, 460 GBytes/sec.
Higher Code Efficiency – replaces multiple issue cores and speculative execution with many more simple CPUs, which are not dependent on the compiler for their efficiency.
Higher Silicon Efficiency than RTL - Re-use gates & memory for multiple functions, performance scales linearly with clock-speed
Broadcast Video Applications
The Algorithms in the GEO Realta Core were refined over 10 years and are field proven in broadcast and post production for the following applications:
DTV Format Conversion
Frame Rate Conversion
2:3 Removal & Insertion
Block Artifact Removal
Mosquito Noise Removal
... and many more
Realta 2 FPGA Core Specs
Massively Parallel Single Instruction Multiple Data (SIMD) Architecture
6144 Processing Elements arranged in 96x64 grid (2x the Realta Chip size)
Core runs at a clock speed of 317 MHz
Each PE has its own data memory, and all PE’s run the same program simultaneously.
2 Trillion Operations per second
The SIMD FPGA is totally scalable in size & speed...
Geo Semiconductor’s Realta 2 Core is poised to revolutionize video processing in FPGA’s. Rather than dedicating a hardware team to painstakingly develop and test new video processing algorithms in dedicated hardware, the Realta SIMD core turns this into a deterministic software development process via our high level C libraries. This streamlines development in three ways:
First, it moves real-time video processing development to the efficient world of software development, providing a >10:1 efficiency improvement.
Second, it provides a platform that is scalable to the requirement by simply changing the array size (no code changes required).
Third, it enables the reduction of the number of SKU’s in a product line, with the only difference between products being the Flash software file that is loaded upon shipment.
The Realta 2 Core is completely customizable, and can meet the most demanding video processing applications, including processing of HD 4k, 8k, and beyond. Best of all, there is a huge library of turnkey, industry proven algorithms along with low level library blocks to build upon.