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ST 2059 FPGA Core

Time Synchronization over IP


Time Synchronization over Internet Protocol

Nextera and Adeas have teamed up to provide a complete solution for standards-based AV over IP. Our fully modular solution consists of FPGA cores, control software, and an end-to-end reference design enabling turn-key development and fast time to market.

The AIP-ST2059 is an FPGA IP core that generates timing and clock signals according to the SMPTE ST 2059 standard defined by the Society of Motion Picture and Television Engineers. These deterministic timing signals can be used to time synchronize audio and video systems to a SMPTE ST 2059 (PTP) grandmaster.

Product Description

The IP core provides broadcast and professional AV equipment the ability to support deterministic generation of timing (signals) for video and audio systems. Audio/visual systems are generally synchronized, locked to the same time base with a relative phase with respect to a master time generator. This makes seamless switching between cameras or mixing a presenter in front of weather graphics possible. The same can be true for audio devices.

The AIP-ST2059 IP core supports timing and synchronization according to the following substandards:

– ST 2059-1: Alignment of Signals to Epoch
– ST 2059-2: Profile for IEEE1588 PTP

AIP-ST2059 uses the IEEE 1588 Precision Time Protocol (PTP) to provide time-aligned signal generation, thus permitting the interoperable use of IP-based media equipment with conventional genlocked SDI equipment.

Based on standard AXI4-Stream, AXI4-Lite and AXI4-MM interfaces, the AIP-ST2059 core can easily be integrated into your system design.

Nextera Video JT-NM Tested
JT-NM Tested

Our Video over IP cores conform to key parts of SMPTE standards with proven interoperability

Nextera Video JT-NM Tested SMPTE ST 2110 2020-1
Nextera Video JT-NM Tested SMPTE ST 2110 2020-2
Nextera Video JT-NM Tested SMPTE ST 2110
Nextera Video JT-NM Tested NMOS TR-1001-1
Nextera Video JT-NM Tested SMPTE ST 2110

Key Features & Benefits

  • Fast locking performance

  • Generation of HH:MM:SS:FF Time Code,

  • Generation of multiple programmable output reference clock and sync signals

  • JT-NM Tested – Implementation is successfully tested during multiple SMPTE and VSF interoperability testing events, earning all possible badges

  • Supports the use of non-PTP aware switches, as well as PTP-aware transparent and boundary clocks

  • The AIP-ST2059 core is network speed independent, so it can be used in 1G, 10G, 25G and 100G Ethernet networks.

Available Demo Designs

  • Based on Xilinx KC705 and KCU105 development kits

  • Supports 1Gb and 10Gb Ethernet networks

  • Generates SDI black frame output and DARS (AES3) output synchronized to the grandmaster

Available Documentations

  • Product guide

  • Application note

Available Licenses

  • Site license

  • Multi-site license

  • Source code license

*A full reference/demo design project is provided along with all of the drivers, daemons, system control software, and a Web GUI so customers can start with a working system and customize to their needs.

Related Products

ST 2110

Click to learn more about SMPTE ST 2110


Click to learn more about NMOS Control Software

SDI Bridge

Click to learn more about SDI Embedder/De-Embedder Subsystem

Reach Us

Corporate Headquarters 1108 Via Treviso, Suite 200
El Dorado Hills, CA 95762

+1 (650) 600-9686

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